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Memory model
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71	Journal of Memory and Language 45, 616–doi:jmla, available online at http://www.academicpress.com on Prime Validity Affects Masked Repetition Priming: Evidence for an Episodic Resource Acco Add to Reading List Source URL: web.uvic.ca Language: English - Date: 2003-07-09 02:27:54 Memory Cognition Psycholinguistics Perception Priming Cognitive biases Lexical decision task Logogen model Structural priming Response priming Transposed letter effect
72	Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-11-03 08:27:59 Computer memory Transaction processing Parallel computing Compiler construction Concurrency Cache coherence Memory ordering Consistency model Linearizability Sequential consistency CPU cache Processor consistency
73	ON TRAINING THE RECURRENT NEURAL NETWORK ENCODER-DECODER FOR LARGE VOCABULARY END-TO-END SPEECH RECOGNITION Liang Lu1 , Xingxing Zhang2 , and Steve Renals1 1 2 Add to Reading List Source URL: homepages.inf.ed.ac.uk Language: English - Date: 2016-01-21 10:21:18 Artificial neural networks Computational neuroscience Computational linguistics Artificial intelligence Computational statistics Recurrent neural network Speech recognition Neural machine translation Long short-term memory Language model Convolutional neural network Vanishing gradient problem
74	Exploiting Communication Concurrency on High Performance Computing Systems Nicholas Chaimov University of Oregon Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2016-02-03 12:11:21 Parallel computing OpenMP Multi-core processor SPMD Unified Parallel C Remote direct memory access Cray Supercomputer Automatic parallelization Thread Blue Gene Parallel programming model
75	Hierarchical Parallelism in a Partitioned Address Space Model Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2012-07-27 09:37:34 Parallel computing Partitioned global address space Manycore processor Non-uniform memory access PGAS SPMD XC Pointer Cell Pascal Barrier
76	Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-10-04 17:36:16 Computer memory Transaction processing Computer architecture Concurrency control Compiler construction Memory ordering Consistency model Cache coherence Memory barrier Linearizability Schedule Sequential consistency
77	IEEE TRANSACTIONS ON AUDIO, SPEECH, AND LANGUAGE PROCESSING, VOL. 16, NO. 2, FEBRUARYSemantic Annotation and Retrieval of Music and Sound Effects Add to Reading List Source URL: eceweb.ucsd.edu Language: English - Date: 2015-07-31 19:00:28 Computational linguistics Natural language processing Machine learning Automatic image annotation Music information retrieval Annotation MPEG-7 Semantic similarity Speech recognition Mixture model Information retrieval Semantic memory
78	Microsoft Word - Post-Silicon Debug__30__group__.doc Add to Reading List Source URL: www.deshawresearch.com Language: English - Date: 2010-09-27 16:06:45 Theoretical computer science Formal methods Integrated circuits Logic in computer science Computer memory Formal verification Waypoint Debugging Application-specific integrated circuit Dynamic random-access memory Error Model checking
79	Structural-RNN: Deep Learning on Spatio-Temporal Graphs Ashesh Jain1,2 , Amir R. Zamir2 , Silvio Savarese2 , and Ashutosh Saxena3 Deep Recurrent Neural Network architectures, though remarkably capable at modeling sequenc Add to Reading List Source URL: cvgl.stanford.edu Language: English - Date: 2016-04-30 18:59:32 Artificial neural networks Graph theory Artificial intelligence Recurrent neural network Computational neuroscience Computational statistics Deep learning Long short-term memory Connectivity Graphical model Graph Directed graph
80	Relaxed memory models must be rigorous ˇ c´ık3 Susmit Sarkar2 Francesco Zappa Nardelli1 Peter Sewell2 Jaroslav Sevˇ Luc Maranget1 Mark Batty2 Jade Alglave1 1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:00 Instruction set architectures Computer memory X86 architecture X86-64 Java memory model X86 Memory barrier Spinlock Memory ordering Low-level programming language Itanium ARM architecture

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